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1 HD66130T 320-channel low-voltage segment driver for dot-matrix stn liquid crystal display description the HD66130T is a 320-channel segment driver for driving a dot-matrix stn liquid-crystal panel at a low voltage. the driver can also correspond to 240-channel output by switching mode. it operates at a low voltage: a liquid-crystal drive voltage of 5 v and a logic drive voltage of 3 v, and is used together with common driver hd66131t or hd66135t. the package, which adopts a flexible tcp, can be applied to various liquid crystal panels. features display duty: up to 1/240 liquid crystal drive voltage: 2.6 to 5.5 v number of liquid crystal drive circuits: 320 circuits operating voltage: 2.5 to 5.5 v number of data bits: 4 or 8 bits shift clock speed: 8 mhz max/5v 6.5 mhz max/3v together with the common drivers hd66131t , hd66135t low power consumption switching output mode: 320 output mode 240 output mode display-off function flexible tcp automatic generation of chip-enable signals standby function
HD66130T 2 pin arrangement 320 y320 2y2 1 y1 319 y319 318 y318 317 y317 316 y316 3y3 4y4 5y5 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 vml v0l v1l v cc mode bs gnd2 shl eio1 disp d0 d1 d2 d3 d4 d5 d6 d7 cl2 cl1 m eio2 gnd1 v1r v0r vmr note: tcp dimensions are not defined. top view internal block diagram note: pins v0l, vml, and v1l are internally connected to pins v0r, vmr, and v1r, respectively. d0?7 cl2 shl eio1 eio2 cl1 vcc gnd2 y 1 ? 320 m disp v0l vml v1l bs mode level shifter latch circuit 2 data rearrangement circuit gnd1 * v0l vml v1l shift register latch circuit 1 latch circuit 1 timing generator circuit level shifter liquid crystal drive circuit
HD66130T 3 1. liquid crystal drive circuit selects and outputs the liquid crystal drive level v0, vm, or v1 by disp and a combination of data for latch circuit 2 and signal m. 2. level shifter converts logic signals to liquid crystal drive signals. 3. latch circuit 2 320-bit latch circuit, which latches the data of latch circuits 1 at the fall of cl1 and outputs the data to the level shifter. 4. latch circuit 1 4/8-bit parallel data latch circuit, which latches display data d0 to d7 according to signals transmitted from the shift register. 5. shift register 80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of cl2. 6. data rearrangement circuit inverts the order of data output crosswise. 7. timing generator circuit the timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the lcd drive outputs to ac. hifas family timing comparision hd66130/131/134/135 hd66132/133 input signal output signal segment common cl1 m
HD66130T 4 pin functions class symbol pin number pin name i/o functions power supply v cc gnd1 gnd2 343 324 340 v cc gnd ? cc ?nd: power supply for logic. v0l, r vml, r v1l, r 345, 322 346, 321 344, 323 v0l, r vml, r v1l, r input liquid crystal drive level power supply v0 vm v1 control signal cl1 327 clock 1 input latch signal of display data: a liquid crystal drive signal corresponding to display data is output at the fall of cl1. cl2 328 clock 2 input capture signal of display data: display data is captured at the fall of cl2. m 326 m input a.c. signal of liquid crystal drive output d0 to d7 336 to 329 data 0 to data 7 input display data liquid crystal drive output liquid crystal display 1 (vcc level) selected level on off not-selected level 0 (gnd level) shl 339 shift left input control signal for inverting the order of data output (see the following page) eio1 338 enable io1 i/o shl gnd vcc enable input enable output enable input enable output ei/o1 ei/o2 eio2 325 enable io2 i/o enable input: the enable input of the first ic is connected to the gnd and another is connected to the enable output of the second ic. enable output: connected to the enable input of the second ic at cascade output. disp 337 disp off input grounding disp sets liquid crystal drive output y1?320 to the vm level. bs 341 bus select input switches the number of input bits for the display data. vcc gnd 8-bit input mode 4-bit input mode (captures data from d0?3. at this time, connect d4?7 to the gnd.) mode 342 mode input switches the number of input bits for the display data. vcc gnd 320 output mode 240 output mode (y41?280 are valid output. the other 80 pins output the not-selected-level signals synchronized every time; release these pins.)
HD66130T 5 pin functions (cont) class symbol pin number pin name i/o function liquid crystal drive output y1 to y320 1 to 320 y1 to y320 output liquid crystal drive output: selects and outputs level v0 or v1 according to the combination of the m signal and display data when disp is connected to vcc. 1 0 11 00 v0 v1 v1 v0 m d output level
HD66130T 6 rearranging output data (shl) the order for the output of captured data is inverted crosswise according to the shl signal. at this time, the input/output pin of the enable signal can be switched. shl = gnd, bs = gnd enable input: eio1 enable output: eio2 first data last data d0 d3 d2 d2 d1 d0 d3 d1 d3 d2 d2 d1 d0 d3 d1 d0 y8 y1 y2 y3 y4 y5 y6 y7 y318 y317 y316 y315 y314 y313 y319 y320 enable input: eio2 enable output: eio1 shl = vcc, bs = gnd last data first data d3 d0 d1 d1 d2 d3 d0 d2 d0 d1 d1 d2 d3 d0 d2 d3 y8 y1 y2 y3 y4 y5 y6 y7 y318 y317 y316 y315 y314 y313 y319 y320 shl = gnd, bs = vcc enable input: eio1 enable output: eio2 first data last data d0 d7 d2 d6 d5 d4 d3 d1 d7 d2 d6 d5 d4 d3 d1 d0 y8 y1 y2 y3 y4 y5 y6 y7 y318 y317 y316 y315 y314 y313 y319 y320 enable input: eio2 enable output: eio1 shl = vcc, bs = vcc last data first data d7 d0 d5 d1 d2 d3 d4 d6 d0 d5 d1 d2 d3 d4 d6 d7 y8 y1 y2 y3 y4 y5 y6 y7 y318 y317 y316 y315 y314 y313 y319 y320
HD66130T 7 operation timing (1) 4-bit capture mode (1 line, 640 dots) d316 d313 12 159 160 cl2 data capture period for ic (no. 1) d0 to d3 cl1 eio2 (no. 1) eio2 (no. 2) line d4 d1 d8 d5 y1?320 d320 d317 81 82 80 79 161 data capture period for ic (no. 2) bs = gnd (4-bit capture mode) during the data standby state when the data capture operation enable signal is low (shl = gnd: eio1 ), the next data capture clock (cl2) cancels the standby state. the 4-bit data is captured at the fall of cl2. when 316 bits are captured, the enable signal becomes the gnd level (shl = gnd: eio2 ). when 320 bits are captured, the operation automatically stops (the standby state is entered). the second ic is then activated when pin eio2 is connected to pin eio1 of the second ic. data output changes at the fall of cl1. during shl = gnd, captured data d1 and d320 are output to y1 and y320, respectively. during shl = vcc, data d1 and d320 are output to y320 and y1, respectively.
HD66130T 8 (2) 8-bit capture mode (1 line, 640 dots) d312 d305 12 79 80 cl2 cl1 line d8 d1 d16 d9 y1?320 d320 d313 41 42 40 39 data capture period for ic (no. 1) eio2 (no. 1) eio2 (no. 2) data capture period for ic (no. 2) d0 to d7 bs = vcc (8-bit capture mode) the 8-bit display data is captured at the fall of cl2. other basic operations are the same as those of the 4- bit capture mode.
HD66130T 9 application example power supply circuit vlcd vh (com) vcc v0 (seg) vm v1 (seg) gnd vl (com) vee lcd panel 640 x 240 1/240 duty controller flm cl1 m disp d0 d7 cl2 vll, r vml, r vhl, r vlcdl, r veel, r dio1 disp shl m gnd cl vcc mode hd66131t y320 to y1 HD66130T y320 to y1 HD66130T x240 to x1 mode bs eio1 disp d0 d7 cl2 cl1 m eio2 gnd1,2 vml, r v0l, r v1l, r com1 com2 com3 com4 com5 com236 com237 com238 com239 com240 seg1 seg2 seg3 seg4 seg5 seg636 seg637 seg638 seg639 seg640 shl vcc mode bs eio1 disp d0 d7 cl2 cl1 m eio2 gnd1,2 vml, r v0l, r v1l, r shl vcc mws4? notes: 1. when designing the board, connect a capacitor near the ic to stabilize power supply. use two capacitors of about 0.1 f for each ic (between vcc and gnd, v0 and gnd, vlcd and gnd, and v ee and gnd). 2. in addition, for the power supply circuit, connect a capacitor of several f or several tens of f between the liquid crystal power supply and gnd. for set evaluation, confirm that there is no inversion of liquid crystal drive power supply and level power supply in the period between when the liquid crystal drive power supply is turned on and when it is turned off. 3. configuring the lcd panel using the hd66130 when using the select common driver. the select common driver common driver select hd66131 (240out) l hd66133 (120out) hd66135 (120out) l
HD66130T 10 absolute maximum ratings item symbol rating unit notes power supply voltage for logic circuits v cc ?.3 to + 7.0 v 1, 4 power supply voltage for lcd drive circuits v0 ?.3 to + 7.0 v 1, 4 input voltage 1 vt1 ?.3 to v cc + 0.3 v 1, 2 input voltage 2 vt2 ?.3 to v0 + 0.3 v 1, 3, 4 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +110 c notes: 1. potential from the gnd 2. applied to pins shl, eio1 , eio2 , disp , d0 to d7, cl1, cl2, m, bs, and mode. 3. applied to vml, vmr, v1l, and vmr. operating the lsi in excess of the absolute maximum rating will result in permanent damage. use the lsi observing electrical characteristic conditions in normal operation. exceeding the conditions will cause malfunctions or will affect lsi reliability. 4. conform to the following turn-on/off sequence of the power and signals. otherwise, the lsi will malfunction or will be permanently damaged. in addition, lsi reliability will be affected. vcc vm v1 input-signal clock data v0 signal-undefined period initialization period (at least one frame) disp 2.7 v 2.7 v 0ms 0ms 0ms 0ms 0ms 0ms vm v1 (0 ms: minimum value)
HD66130T 11 4.1 turning on the power 1) turn on the power in the order of gnd- v cc , gnd-v0, and vm/v1. then, ground the disp pin. 2) the lcd forcibly outputs the vm level by the dispoff function. 3) even if an input signal is disturbed immediately after v cc is applied, the dispoff function has priority. 4) input the specific signal to initialize registers in the driver. the initialization period must be at least one frame. 5) the preparation of normal display is completed. input the v cc level to the disp pin to cancel the dispoff function. at this time, the level of pins v0, vm, and v1 must rise to the specific potential. 4.2 turning off the power the procedure is basically the reverse for turning on the power. 1) ground the disp pin. 2) turn off the liquid crystal power in the order of vm/v1 and gnd-v0. 3) ground v cc and an input signal. at this time, the level of pins v0, vm, and v1 must fall to 0 v. since the dispoff function stops when v cc falls to 0 v, the lcd may output a level other than vm. therefore, a display failure may occur when the power is turned off or on.
HD66130T 12 electrical characteristics dc characteristics 1 (v cc = 2.5 to 4.5v, v0?nd = 2.6 to 5.5v, ta = ?0 to +75 c) item symbol pins min typ max unit test condition notes input high voltage vih cl1, cl2, shl, m, eio1 , eio2 , 0.8 v cc ? cc v input low voltage vil mode, disp , d0 to d7, bs 0 0.2 v cc v output high voltage voh eio1 , eio2 v cc ?.4 v i oh = ?.4 ma output low voltage vol eio1 , eio2 0.4 v i ol = 0.4 ma vi?j on resistance r on y1 to y320, v0l, r 0.7 2.0 k w i on = 150 m a1 y1 to y320, vml, r 2.0 3.0 k w y1 to y320, v1l, r 0.7 2.0 k w input leakage current 1 i il1 cl1, cl2, shl, m, eio1 , eio2 , mode, disp , d0 to d7, bs ?.0 5.0 m a vin = v cc to gnd input leakage current 2 i il2 vml, r, v1l, r ?5 25 m a vin = v0 to gnd current consumption 1 i cc v cc 150 300 m av cc = 3.3 v v0 = 2.7 v 2 current consumption 2 iv0 v0l, r 60 200 m af cl2 = 3.5 mhz f cl1 = 19.2 khz current consumption 3 i st v cc 50 100 m a fm = 1.5 khz 2, 3
HD66130T 13 dc characteristics 2 (v cc = 4.5 to 5.5v, v0?nd = 2.6 to 5.5v, ta = ?0 to +75 c) item symbol pins min typ max unit test condition notes input high voltage vih cl1, cl2, shl, m, eio1 , eio2 , 0.8 v cc ? cc v input low voltage vil mode, disp , d0 to d7, bs 0 0.2 v cc v output high voltage voh eio1 , eio2 v cc ?.4 v i oh = ?.4 ma output low voltage vol eio1 , eio2 0.4 v i ol = 0.4 ma vi?j on resistance r on y1 to y320, v0l, r 0.7 2.0 k w i on = 150 m a1 y1 to y320, vml, r 2.0 3.0 k w y1 to y320, v1l, r 0.7 2.0 k w input leakage current 1 i il1 cl1, cl2, shl, m, eio1 , eio2 , mode, disp , d0 to d7, bs ?.0 5.0 m a vin = v cc to gnd input leakage current 2 i il2 vml, r, v1l, r ?5 25 m a vin = v0 to gnd current consumption 1 i cc v cc 230 450 m av cc = 5.0 v v0 = 2.7 v 2 current consumption 2 iv0 v0l, r 60 200 m af cl2 = 3.5 mhz f cl1 = 19.2 khz current consumption 3 i st v cc 80 150 m a fm = 1.5 khz 2, 3 notes: 1. resistance between pins y and v when a load current flows to one of the pins from y1 to y320. the following conditions are defined: v0?nd = 5.5 v vm = (v0 + v1)/2
HD66130T 14 v1 = gnd + 1.0 the voltage range of the liquid crystal drive level power supply is described. a voltage around the gnd is applied to pin v1, and an intermediate voltage of about v0 and v1 is applied to pin vm. use the v1 in the range of d v = 0.25 x v0, in which the impedance ron of driver output is stable. v0 gnd vm v1 ? v = 0.25 x v0 relationship between the driver output waveform and each level voltage 2. a current flowing in the input or output section is excluded. if an input signal is at an intermediate level for the cmos, a through-current flows in the input circuit and power supply current increases. therefore, vih must be at the vcc level and vil must be at the gnd level. 3. current at standby 4. the voltage of each signal is shown below. gnd (0.0 v) vcc (3.3 v) v1 (1.0 v) vm (3.0 v) v0 (5.0 v) vl (?7.0 v) vh (23.0 v) vm (3.0 v) display-off period normal display period segment voltage segment waveform common voltage common waveform gnd (0.0 v) vcc (3.3 v) normal display period display-off period
HD66130T 15 ac characteristics 1 (v cc = 2.5 to 4.5v, v0?nd = 2.6 to 5.5v, ta = ?0 to +75 c) item symbol pins min max unit clock cycle time t cyc cl2 152 ns clock high pulse width 1 t cwh2 cl2 65 ns clock low pulse width 1 t cwl2 cl2 65 ns clock high pulse width 2 t cwh1 cl1 65 ns clock setup time t scl cl1, cl2 80 ns clock hold time t hcl cl1, cl2 80 ns clock rise time t r cl1, cl2 30 ns clock fall time t f cl1, cl2 30 ns data setup time t ds d0 to d7, cl2 50 ns data hold time t dh d0 to d7, cl2 50 ns m setup time t ms m, cl1 20 ns m hold time t mh m, cl1 20 ns output delay time 1 t pd1 cl1, y1 to y320 1000 ns ac characteristics 2 (v cc = 4.5v to 5.5v, v0?nd = 2.6 to 5.5v, ta = ?0 to +75 c) item symbol pins min max unit clock cycle time t cyc cl2 125 ns clock high pulse width 1 t cwh2 cl2 45 ns clock low pulse width 1 t cwl2 cl2 45 ns clock high pulse width 2 t cwh1 cl1 45 ns clock setup time t scl cl1, cl2 80 ns clock hold time t hcl cl1, cl2 80 ns clock rise time t r cl1, cl2 20 ns clock fall time t f cl1, cl2 20 ns data setup time t ds d0 to d7, cl2 20 ns data hold time t dh d0 to d7, cl2 20 ns m setup time t ms m, cl1 20 ns m hold time t mh m, cl1 20 ns output delay time 1 t pd1 cl1, y1 to y320 1000 ns notes: 1. a load must be 10 pf or less for ei/o connection between drivers. 2. for output delay time 1 and 2, connect the load circuit shown below. test point 100 pf
HD66130T 16 cl2 d0? tr t cwh2 tf t cwl2 t cyc t ds t dh 0.8 vcc 0.2 vcc 0.8 vcc 0.2 vcc y (n) cl1 t pd1 0.2 vcc 0.8 v0 0.2 v1 0.8 vcc 0.2 vcc m t ms cl1 cl2 t scl t hcl 0.8 vcc 0.2 vcc 0.2 vcc t cwh1 t mh

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